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RISC-V: Add test for vec_duplicate + vwmulu.vv signed combine with GR2VR cost 0, 1 and 15

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Add asm dump check and run test for vec_duplicate + vwmulu.vv
combine to vwmulu.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
	for vwmulu.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: Add test helper
	macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: Add test
	data for vwmulu.vx run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li
2025-09-12 21:43:52 +08:00
parent f3d6d41abf
commit f666b14cf1
12 changed files with 69 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
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@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
/* { dg-final { scan-assembler-not {vwsubu.vx} } } */
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

1
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
View File

@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
/* { dg-final { scan-assembler-not {vwsubu.vx} } } */
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

1
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
View File

@@ -34,3 +34,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vwaddu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vwsubu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vwmulu.vx} 1 } } */

1
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
View File

@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
/* { dg-final { scan-assembler-not {vwsubu.vx} } } */
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

1
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
View File

@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
/* { dg-final { scan-assembler-not {vwsubu.vx} } } */
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

1
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
View File

@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
/* { dg-final { scan-assembler-not {vwsubu.vx} } } */
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

1
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
View File

@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
/* { dg-final { scan-assembler-not {vwsubu.vx} } } */
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

1
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
View File

@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
/* { dg-final { scan-assembler-not {vwsubu.vx} } } */
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

1
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
View File

@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.vx} } } */
/* { dg-final { scan-assembler-not {vwsubu.vx} } } */
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

18
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c Normal file
View File

@@ -0,0 +1,18 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
#include "vx_widen.h"
#include "vx_widen_data.h"
#define WT uint64_t
#define NT uint32_t
#define NAME mul
#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME)
#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME)
DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, *, NAME)
#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \
RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, N)
#include "vx_widen_vx_run.h"

3
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
View File

@@ -30,6 +30,7 @@ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_0 (WT * restrict vd, \
#define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT) \
DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add) \
DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub)
DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub) \
DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, *, mul) \
#endif

40
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
View File

@@ -37,6 +37,7 @@
DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, add)
DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, sub)
DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, mul)
DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = {
{
@@ -116,4 +117,43 @@ DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, sub)[] = {
},
};
DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, mul)[] = {
{
/* vs2 */
{
1, 1, 1, 1,
0, 0, 0, 0,
2, 2, 2, 2,
9, 9, 9, 9,
},
/* rs1 */
2147483647,
/* expect */
{
2147483647, 2147483647, 2147483647, 2147483647,
0, 0, 0, 0,
4294967294, 4294967294, 4294967294, 4294967294,
19327352823ull, 19327352823ull, 19327352823ull, 19327352823ull,
},
},
{
/* vs2 */
{
1, 1, 1, 1,
0, 0, 0, 0,
4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull,
4294967294ull, 4294967294ull, 4294967294ull, 4294967294ull,
},
/* rs1 */
4294967295,
/* expect */
{
4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull,
0, 0, 0, 0,
18446744065119617025ull, 18446744065119617025ull, 18446744065119617025ull, 18446744065119617025ull,
18446744060824649730ull, 18446744060824649730ull, 18446744060824649730ull, 18446744060824649730ull,
},
},
};
#endif