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i386: Fix dot_prod backend patterns for mmx and sse targets
Following the migration of the dot_prod optab from a direct to a conversion-type optab, ensure all back-end patterns incorporate the second machine mode into pattern names. gcc/ChangeLog: * config/i386/mmx.md (usdot_prodv8qi): Renamed to... (usdot_prodv2siv8qi): ...this. (sdot_prodv8qi): Renamed to... (sdot_prodv2siv8qi): ...this. (udot_prodv8qi): Renamed to... (udot_prodv2siv8qi): ...this. (usdot_prodv4hi): Renamed to... (usdot_prodv2siv4hi): ...this. (udot_prodv4hi): Renamed to... (udot_prodv2siv4hi): ...this. (sdot_prodv4hi): Renamed to... (sdot_prodv2siv4hi): ...this. * config/i386/sse.md (sdot_prod<mode>): Renamed to... (sdot_prod<sseunpackmodelower><mode>): ...this. (sdot_prodv4si): Renamed to... (sdot_prodv2div4si): ...this. (usdot_prod<mode>): Renamed to... (usdot_prod<ssedvecmodelower><mode>): ...this. (sdot_prod<mode>): Renamed to... (sdot_prod<ssedvecmodelower><mode>): ...this. (sdot_prodv64qi): Renamed to... (sdot_prodv16siv64qi): ...this. (udot_prod<mode>): Renamed to... (udot_prod<ssedvecmodelower><mode>): ...this. (udot_prodv64qi): Renamed to... (udot_prodv16qiv64qi): ...this. (usdot_prod<mode>): Renamed to... (usdot_prod<sseunpackmodelower><mode>): ...this. (udot_prod<mode>): Renamed to... (udot_prod<sseunpackmodelower><mode>): ...this.
This commit is contained in:
Victor Do Nascimento
@@ -6504,7 +6504,7 @@
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DONE;
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})
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(define_expand "usdot_prodv8qi"
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(define_expand "usdot_prodv2siv8qi"
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[(match_operand:V2SI 0 "register_operand")
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(match_operand:V8QI 1 "register_operand")
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(match_operand:V8QI 2 "register_operand")
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@@ -6523,7 +6523,7 @@
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rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
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rtx op0 = gen_reg_rtx (V4SImode);
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emit_insn (gen_usdot_prodv16qi (op0, op1, op2, op3));
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emit_insn (gen_usdot_prodv4siv16qi (op0, op1, op2, op3));
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emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
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}
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else
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@@ -6537,7 +6537,7 @@
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emit_move_insn (op3, CONST0_RTX (V4SImode));
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emit_insn (gen_zero_extendv8qiv8hi2 (op1, operands[1]));
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emit_insn (gen_extendv8qiv8hi2 (op2, operands[2]));
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emit_insn (gen_sdot_prodv8hi (op0, op1, op2, op3));
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emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
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/* vec_perm (op0, 2, 3, 0, 1); */
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emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78)));
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@@ -6548,7 +6548,7 @@
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DONE;
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})
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(define_expand "sdot_prodv8qi"
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(define_expand "sdot_prodv2siv8qi"
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[(match_operand:V2SI 0 "register_operand")
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(match_operand:V8QI 1 "register_operand")
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(match_operand:V8QI 2 "register_operand")
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@@ -6566,7 +6566,7 @@
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rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
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rtx op0 = gen_reg_rtx (V4SImode);
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emit_insn (gen_sdot_prodv16qi (op0, op1, op2, op3));
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emit_insn (gen_sdot_prodv4siv16qi (op0, op1, op2, op3));
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emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
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}
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else
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@@ -6580,7 +6580,7 @@
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emit_move_insn (op3, CONST0_RTX (V4SImode));
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emit_insn (gen_extendv8qiv8hi2 (op1, operands[1]));
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emit_insn (gen_extendv8qiv8hi2 (op2, operands[2]));
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emit_insn (gen_sdot_prodv8hi (op0, op1, op2, op3));
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emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
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/* vec_perm (op0, 2, 3, 0, 1); */
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emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78)));
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@@ -6592,7 +6592,7 @@
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})
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(define_expand "udot_prodv8qi"
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(define_expand "udot_prodv2siv8qi"
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[(match_operand:V2SI 0 "register_operand")
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(match_operand:V8QI 1 "register_operand")
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(match_operand:V8QI 2 "register_operand")
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@@ -6610,7 +6610,7 @@
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rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
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rtx op0 = gen_reg_rtx (V4SImode);
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emit_insn (gen_udot_prodv16qi (op0, op1, op2, op3));
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emit_insn (gen_udot_prodv4siv16qi (op0, op1, op2, op3));
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emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
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}
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else
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@@ -6624,7 +6624,7 @@
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emit_move_insn (op3, CONST0_RTX (V4SImode));
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emit_insn (gen_zero_extendv8qiv8hi2 (op1, operands[1]));
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emit_insn (gen_zero_extendv8qiv8hi2 (op2, operands[2]));
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emit_insn (gen_sdot_prodv8hi (op0, op1, op2, op3));
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emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
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/* vec_perm (op0, 2, 3, 0, 1); */
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emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78)));
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@@ -6636,7 +6636,7 @@
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})
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(define_expand "usdot_prodv4hi"
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(define_expand "usdot_prodv2siv4hi"
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[(match_operand:V2SI 0 "register_operand")
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(match_operand:V4HI 1 "register_operand")
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(match_operand:V4HI 2 "register_operand")
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@@ -6652,12 +6652,12 @@
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rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
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rtx op0 = gen_reg_rtx (V4SImode);
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emit_insn (gen_usdot_prodv8hi (op0, op1, op2, op3));
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emit_insn (gen_usdot_prodv4siv8hi (op0, op1, op2, op3));
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emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
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DONE;
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})
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(define_expand "udot_prodv4hi"
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(define_expand "udot_prodv2siv4hi"
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[(match_operand:V2SI 0 "register_operand")
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(match_operand:V4HI 1 "register_operand")
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(match_operand:V4HI 2 "register_operand")
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@@ -6673,12 +6673,12 @@
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rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
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rtx op0 = gen_reg_rtx (V4SImode);
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emit_insn (gen_udot_prodv8hi (op0, op1, op2, op3));
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emit_insn (gen_udot_prodv4siv8hi (op0, op1, op2, op3));
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emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
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DONE;
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})
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(define_expand "sdot_prodv4hi"
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(define_expand "sdot_prodv2siv4hi"
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[(match_operand:V2SI 0 "register_operand")
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(match_operand:V4HI 1 "register_operand")
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(match_operand:V4HI 2 "register_operand")
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@@ -6694,7 +6694,7 @@
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rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
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rtx op0 = gen_reg_rtx (V4SImode);
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emit_insn (gen_sdot_prodv8hi (op0, op1, op2, op3));
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emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
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emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
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DONE;
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})
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@@ -16975,7 +16975,7 @@
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(define_mode_attr SDOT_VPDP_SUF
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[(V32HI "v16si") (V16HI "v8si") (V8HI "v4si")])
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(define_expand "sdot_prod<mode>"
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(define_expand "sdot_prod<sseunpackmodelower><mode>"
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[(match_operand:<sseunpackmode> 0 "register_operand")
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(match_operand:VI2_AVX512VNNIBW 1 "register_operand")
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(match_operand:VI2_AVX512VNNIBW 2 "register_operand")
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@@ -17010,7 +17010,7 @@
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;; Normally we use widen_mul_even/odd, but combine can't quite get it all
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;; back together when madd is available.
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(define_expand "sdot_prodv4si"
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(define_expand "sdot_prodv2div4si"
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[(match_operand:V2DI 0 "register_operand")
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(match_operand:V4SI 1 "register_operand")
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(match_operand:V4SI 2 "register_operand")
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@@ -30471,7 +30471,7 @@
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[(set_attr ("prefix") ("evex"))
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(set_attr "mode" "<sseinsnmode>")])
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(define_expand "usdot_prod<mode>"
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(define_expand "usdot_prod<ssedvecmodelower><mode>"
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[(match_operand:<ssedvecmode> 0 "register_operand")
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(match_operand:VI1_AVX512 1 "register_operand")
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(match_operand:VI1_AVX512 2 "register_operand")
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@@ -30509,10 +30509,11 @@
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rtx sum = gen_reg_rtx (<ssedvecmode>mode);
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emit_move_insn (sum, CONST0_RTX (<ssedvecmode>mode));
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emit_insn (gen_sdot_prod<sseunpackmodelower> (res1, op1_lo,
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op2_lo, sum));
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emit_insn (gen_sdot_prod<sseunpackmodelower> (res2, op1_hi,
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op2_hi, operands[3]));
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emit_insn (gen_sdot_prod<ssedvecmodelower><sseunpackmodelower> (res1,
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op1_lo, op2_lo, sum));
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emit_insn (gen_sdot_prod<ssedvecmodelower><sseunpackmodelower> (res2,
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op1_hi, op2_hi,
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operands[3]));
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emit_insn (gen_add<ssedvecmodelower>3 (operands[0], res1, res2));
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}
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DONE;
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@@ -31336,7 +31337,7 @@
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(UNSPEC_VPDPBSUD "bsud") (UNSPEC_VPDPBSUDS "bsuds")
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(UNSPEC_VPDPBUUD "buud") (UNSPEC_VPDPBUUDS "buuds")])
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(define_expand "sdot_prod<mode>"
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(define_expand "sdot_prod<ssedvecmodelower><mode>"
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[(match_operand:<ssedvecmode> 0 "register_operand")
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(match_operand:VI1_AVX512VNNIBW 1 "register_operand")
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(match_operand:VI1_AVX512VNNIBW 2 "register_operand")
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@@ -31373,17 +31374,18 @@
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rtx sum = gen_reg_rtx (<ssedvecmode>mode);
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emit_move_insn (sum, CONST0_RTX (<ssedvecmode>mode));
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emit_insn (gen_sdot_prod<sseunpackmodelower> (res1, op1_lo,
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op2_lo, sum));
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emit_insn (gen_sdot_prod<sseunpackmodelower> (res2, op1_hi,
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op2_hi, operands[3]));
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emit_insn (gen_sdot_prod<ssedvecmodelower><sseunpackmodelower> (res1,
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op1_lo, op2_lo, sum));
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emit_insn (gen_sdot_prod<ssedvecmodelower><sseunpackmodelower> (res2,
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op1_hi, op2_hi,
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operands[3]));
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emit_insn (gen_add<ssedvecmodelower>3 (operands[0], res1, res2));
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}
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DONE;
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})
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(define_expand "udot_prod<mode>"
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(define_expand "udot_prod<ssedvecmodelower><mode>"
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[(match_operand:<ssedvecmode> 0 "register_operand")
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(match_operand:VI1_AVX512VNNIBW 1 "register_operand")
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(match_operand:VI1_AVX512VNNIBW 2 "register_operand")
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@@ -31420,10 +31422,11 @@
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rtx sum = gen_reg_rtx (<ssedvecmode>mode);
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emit_move_insn (sum, CONST0_RTX (<ssedvecmode>mode));
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emit_insn (gen_sdot_prod<sseunpackmodelower> (res1, op1_lo,
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op2_lo, sum));
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emit_insn (gen_sdot_prod<sseunpackmodelower> (res2, op1_hi,
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op2_hi, operands[3]));
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emit_insn (gen_sdot_prod<ssedvecmodelower><sseunpackmodelower> (res1,
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op1_lo, op2_lo, sum));
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emit_insn (gen_sdot_prod<ssedvecmodelower><sseunpackmodelower> (res2,
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op1_hi, op2_hi,
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operands[3]));
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emit_insn (gen_add<ssedvecmodelower>3 (operands[0], res1, res2));
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}
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@@ -31803,7 +31806,7 @@
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(UNSPEC_VPDPWSUD "wsud") (UNSPEC_VPDPWSUDS "wsuds")
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(UNSPEC_VPDPWUUD "wuud") (UNSPEC_VPDPWUUDS "wuuds")])
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(define_expand "usdot_prod<mode>"
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(define_expand "usdot_prod<sseunpackmodelower><mode>"
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[(match_operand:<sseunpackmode> 0 "register_operand")
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(match_operand:VI2_AVX10_2 1 "register_operand")
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(match_operand:VI2_AVX10_2 2 "register_operand")
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@@ -31821,7 +31824,7 @@
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DONE;
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})
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(define_expand "udot_prod<mode>"
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(define_expand "udot_prod<sseunpackmodelower><mode>"
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[(match_operand:<sseunpackmode> 0 "register_operand")
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(match_operand:VI2_AVX10_2 1 "register_operand")
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(match_operand:VI2_AVX10_2 2 "register_operand")
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