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MIPS/testsuite: Use isa_rev=2 instead of >=2

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So that they won't fail for r6 targets.

gcc/testsuite/ChangeLog:
	* gcc.target/mips/mips16e2.c: Use isa_rev=2 instead of >=2.
	* gcc.target/mips/mips16e2-cache.c: Ditto.
	* gcc.target/mips/mips16e2-cmov.c: Ditto.
	* gcc.target/mips/mips16e2-gp.c: Ditto.
This commit is contained in:
YunQiang Su
2025-09-27 22:24:49 +08:00
committed by YunQiang Su
parent b07bab1953
commit 10bb371eee
4 changed files with 4 additions and 4 deletions
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2
gcc/testsuite/gcc.target/mips/mips16e2-cache.c
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@@ -1,4 +1,4 @@
/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */
/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev=2 -mmips16e2" } */
/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
/* Test cache. */

2
gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
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@@ -1,4 +1,4 @@
/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2 -mbranch-cost=2" } */
/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev=2 -mmips16e2 -mbranch-cost=2" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
/* Test MOVN. */

2
gcc/testsuite/gcc.target/mips/mips16e2-gp.c
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@@ -1,4 +1,4 @@
/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */
/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev=2 -mmips16e2" } */
/* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */
/* Generate GP-relative ADDIU. */

2
gcc/testsuite/gcc.target/mips/mips16e2.c
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@@ -1,4 +1,4 @@
/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */
/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev=2 -mmips16e2" } */
/* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */
/* ANDI is a two operand instruction. Hence, it won't be generated if src and