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LoongArch: guard SImode simple shift and arithmetic expansions with can_create_pseudo_p [PR 123320]
As we have hardware instructions for those operations, developers will reasonably assume they can emit them even after reload. But on LA64 we are expanding them using pseudos to reduce unneeded sign extensions, breaking such an expectation and causing ICE like PR 123320. Only create the pseudo when can_create_pseudo_p () to fix such cases. PR target/123320 gcc * config/loongarch/loongarch.md (<optab><mode>3): Only expand using psuedos when can_create_pseudo_p (). (addsi3): Likewise. gcc/testsuite * gcc.target/loongarch/la64/pr123320.c: New test.
This commit is contained in:
Xi Ruoyao
@@ -648,7 +648,7 @@
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(match_operand:SI 2 "arith_operand" "rI")))]
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""
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{
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if (TARGET_64BIT && <MODE>mode == SImode)
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if (TARGET_64BIT && <MODE>mode == SImode && can_create_pseudo_p ())
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{
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rtx t = gen_reg_rtx (DImode);
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emit_insn (gen_<optab>si3_extend (t, operands[1], operands[2]));
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@@ -666,7 +666,7 @@
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(match_operand:GPR 2 "register_operand" "r")))]
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""
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{
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if (TARGET_64BIT && <MODE>mode == SImode)
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if (TARGET_64BIT && <MODE>mode == SImode && can_create_pseudo_p ())
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{
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rtx t = gen_reg_rtx (DImode);
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emit_insn (gen_<optab>si3_extend (t, operands[1], operands[2]));
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@@ -751,7 +751,7 @@
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(match_operand:SI 2 "plus_si_operand" "r,I,La,Le,Lb")))]
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""
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{
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if (TARGET_64BIT)
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if (TARGET_64BIT && can_create_pseudo_p ())
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{
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if (CONST_INT_P (operands[2]) && !IMM12_INT (operands[2])
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&& ADDU16I_OPERAND (INTVAL (operands[2])))
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@@ -1066,7 +1066,8 @@
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(match_operand:GPR 2 "register_operand")))]
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""
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{
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if (GET_MODE (operands[0]) == SImode && TARGET_64BIT)
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if (GET_MODE (operands[0]) == SImode && TARGET_64BIT
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&& can_create_pseudo_p ())
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{
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if (ISA_HAS_DIV32)
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{
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128
gcc/testsuite/gcc.target/loongarch/la64/pr123320.c
Normal file
128
gcc/testsuite/gcc.target/loongarch/la64/pr123320.c
Normal file
@@ -0,0 +1,128 @@
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/* PR 123320: ICE in peephole2 */
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/* { dg-do compile } */
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/* { dg-options "-Os -mlsx -fstack-protector -w" } */
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typedef char a;
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typedef short b;
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typedef int c;
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typedef long d;
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typedef char e;
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typedef short f;
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typedef int g;
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f h;
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struct i {
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signed j : 20
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} * k;
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c l, m, n;
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a o;
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static struct i p[][5];
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static struct i q;
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d r, s;
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__attribute__((__vector_size__(32))) a t;
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g __attribute__((vector_size(16)))
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u(f __attribute__((vector_size(2 * sizeof(f)))),
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b __attribute__((vector_size(16 * sizeof(b)))), e);
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c __attribute__((vector_size(8 * sizeof(c))))
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v(e __attribute__((vector_size(2))), a,
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d __attribute__((vector_size(2 * sizeof(d)))),
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e __attribute__((vector_size(16))), a __attribute__((vector_size(32))),
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f __attribute__((vector_size(16 * sizeof(f)))));
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f(w)(f x) { return x - h; }
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void y(int);
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void z(g, g, f, struct i);
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static c aa(struct i ab, struct i ac)
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{
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a __attribute__((vector_size(8))) ad;
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for (; l;)
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{
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__asm("" ::: "$r31");
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r = w(0 == ab.j);
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ac.j = ab.j;
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ab.j = ad[0] =
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v((e __attribute__((vector_size(2)))){}, 0,
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(d __attribute__((vector_size(2 * sizeof(d))))){},
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(e __attribute__((vector_size(16)))){},
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(a __attribute__((vector_size(32)))){},
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~__builtin_shufflevector(
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__builtin_shufflevector(
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(f __attribute__((vector_size(16 *sizeof(f))))){},
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__builtin_convertvector(
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__builtin_shufflevector(t, t, 9, 2, 9, 6, 3, 6, 2, 2,
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8, 8, 2, 7, 3, 0, 5, 0),
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f __attribute__((vector_size(16 * sizeof(f))))),
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25, 8, 1, 8, 9, 1, 7, 2, 5, 2, 0, 4, 8, 1, 9, 0, 6, 3, 3,
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7, 1, 6, 2, 0, 5, 1, 3, 5, 0, 1, 4, 6),
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(f __attribute__((vector_size(sizeof(f))))){}, 9, 1, 4, 4, 0,
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2, 5, 2, 8, 6, 3, 8, 4, 1, 4, 9))[3];
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}
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if (ac.j)
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__builtin_convertvector(
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__builtin_shufflevector(
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v(__builtin_convertvector(__builtin_shufflevector(ad, ad, 2, 2),
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e __attribute__((vector_size(2)))),
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0, (d __attribute__((vector_size(2 * sizeof(d))))){},
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(e __attribute__((vector_size(16)))){},
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(a __attribute__((vector_size(32)))){},
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(f __attribute__((vector_size(16 * sizeof(f))))){}),
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v(__builtin_convertvector(__builtin_shufflevector(ad, ad, 2, 2),
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e __attribute__((vector_size(2)))),
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0, (d __attribute__((vector_size(2 * sizeof(d))))){},
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(e __attribute__((vector_size(16)))){},
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(a __attribute__((vector_size(32)))){},
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(f __attribute__((vector_size(16 * sizeof(f))))){}),
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2, 6, 0, 6),
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a __attribute__((vector_size(4))));
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}
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void ae()
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{
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int af = 0;
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if (m) af = 1;
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struct i ag;
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(g __attribute__((vector_size(sizeof(
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g))))){}[u((f __attribute__((vector_size(2 *sizeof(f))))){},
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(b __attribute__((vector_size(16 * sizeof(b))))){}, 0)[2]
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? u((f __attribute__((vector_size(2 *sizeof(f))))){},
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(b __attribute__((vector_size(16 * sizeof(b))))){},
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0)[2]
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: 0];
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a __attribute__((vector_size(2))) ah;
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ag.j == o;
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__asm("" ::: "$r26");
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__asm("" ::: "$r30", "$r23");
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__builtin_convertvector(
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__builtin_shufflevector(
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v(__builtin_shufflevector(
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__builtin_convertvector(
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__builtin_shufflevector(ah, ah, 3, 2, 0, 3),
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e __attribute__((vector_size(4)))),
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(e __attribute__((vector_size(4)))){}, 2, 6),
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0, (d __attribute__((vector_size(2 * sizeof(d))))){},
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(e __attribute__((vector_size(16)))){},
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(a __attribute__((vector_size(32)))){},
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__builtin_convertvector(
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__builtin_shufflevector(ah, ah, 3, 0, 3, 3, 0, 1, 0, 1, 1, 3,
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1, 1, 2, 1, 2, 2),
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f __attribute__((vector_size(16 * sizeof(f)))))),
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v(__builtin_shufflevector(
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__builtin_convertvector(
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__builtin_shufflevector(ah, ah, 3, 2, 0, 3),
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e __attribute__((vector_size(4)))),
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(e __attribute__((vector_size(4)))){}, 2, 6),
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0, (d __attribute__((vector_size(2 * sizeof(d))))){},
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(e __attribute__((vector_size(16)))){},
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(a __attribute__((vector_size(32)))){},
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__builtin_convertvector(
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__builtin_shufflevector(ah, ah, 3, 0, 3, 3, 0, 1, 0, 1, 1, 3,
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1, 1, 2, 1, 2, 2),
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f __attribute__((vector_size(16 * sizeof(f)))))),
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3, 2, 1, 0, 8, 6, 3, 2, 5, 2, 0, 2, 2, 3, 1, 0, 2, 6, 5, 6, 9, 6, 0,
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2, 4, 2, 5, 1, 4, 4, 6, 0),
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b __attribute__((vector_size(32 * sizeof(b)))));
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__asm goto("" : : : : ai);
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ag = *k;
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ai:
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aa(ag, p[5][4]);
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z(n, s, s, q);
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y(af);
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}
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