mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

This patch fixes the backend pattern that was printing the wrong input
scalar register pair when inserting into lane 1.

Added a new test to force float-abi=hard so we can use scan-assembler to check
correct codegen.

gcc/ChangeLog:

	PR target/115611
	* config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of input
	scalar register pair when lane = 1.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c: New test.

(cherry picked from commit 7c11fdd2cc)

gcc/config/arm/mve.md

@@ -10510,7 +10510,7 @@
   if (elt == 0)
    return "vmov\t%e0, %Q1, %R1";
   else
-   return "vmov\t%f0, %J1, %K1";
+   return "vmov\t%f0, %Q1, %R1";
 }
  [(set_attr "type" "mve_move")])
 

gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c

@@ -0,0 +1,63 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-require-effective-target arm_hard_ok } */
+/* { dg-additional-options "-mfloat-abi=hard -O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_mve.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**fn1:
+**	vmov	d0, r0, r1
+**	bx	lr
+*/
+uint64x2_t
+fn1 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 0);
+}
+
+/*
+**fn2:
+**	vmov	d1, r0, r1
+**	bx	lr
+*/
+uint64x2_t
+fn2 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 1);
+}
+
+/*
+**fn3:
+**	vmov	d0, r0, r1
+**	bx	lr
+*/
+int64x2_t
+fn3 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 0);
+}
+
+/*
+**fn4:
+**	vmov	d1, r0, r1
+**	bx	lr
+*/
+int64x2_t
+fn4 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 1);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+