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RISC-V: Refine the testcase of vector SAT_SUB

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Take scan-assembler-times for vssub insn check instead of function body,
as we only care about if we can generate the fixed point insn vssub.

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Remove
	func body check and take scan asm times instead.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li
2024-09-25 13:55:22 +08:00
parent 043d607cc4
commit 32bcca3e58
44 changed files with 92 additions and 496 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint8_t_fmt_1:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_1(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint16_t_fmt_3:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_3(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint32_t_fmt_3:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_3(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint64_t_fmt_3:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_3(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint8_t_fmt_4:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_4(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint16_t_fmt_4:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_4(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint32_t_fmt_4:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_4(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint64_t_fmt_4:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_4(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint8_t_fmt_5:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_5(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint16_t_fmt_5:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_5(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint32_t_fmt_5:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_5(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint16_t_fmt_1:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_1(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint64_t_fmt_5:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_5(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint8_t_fmt_6:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_6(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint16_t_fmt_6:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_6(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint32_t_fmt_6:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_6(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint64_t_fmt_6:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_6(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint8_t_fmt_7:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_7(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint16_t_fmt_7:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_7(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint32_t_fmt_7:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_7(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint64_t_fmt_7:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_7(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint8_t_fmt_8:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_8(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint32_t_fmt_1:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_1(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint16_t_fmt_8:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_8(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint32_t_fmt_8:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_8(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint64_t_fmt_8:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_8(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint8_t_fmt_9:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_9(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint16_t_fmt_9:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_9(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint32_t_fmt_9:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_9(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint64_t_fmt_9:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_9(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint8_t_fmt_10:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_10(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint16_t_fmt_10:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_10(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint32_t_fmt_10:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_10(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint64_t_fmt_1:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_1(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint64_t_fmt_10:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_10(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint8_t_fmt_2:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_2(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint16_t_fmt_2:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_2(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint32_t_fmt_2:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_2(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint64_t_fmt_2:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_2(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
View File

@@ -1,18 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint8_t_fmt_3:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_FMT_3(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */

18
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
View File

@@ -1,22 +1,10 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_trunc_uint8_t_fmt_1:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
** ...
** vsetvli\s+zero,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
** ...
** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */

18
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
View File

@@ -1,22 +1,10 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_trunc_uint16_t_fmt_1:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
** ...
** vsetvli\s+zero,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
** ...
** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */

18
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
View File

@@ -1,22 +1,10 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_trunc_uint32_t_fmt_1:
** ...
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
** ...
** vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
** ...
** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */

14
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c
View File

@@ -1,18 +1,10 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
/*
** vec_sat_u_sub_uint16_t_uint32_t_fmt_zip:
** ...
** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
** ...
** vrgather\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
*/
DEF_VEC_SAT_U_SUB_ZIP_WRAP(uint16_t, uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */