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Add asm dump check test for vec_duplicate + vssub.vv combine to vssub.vx, with the GR2VR cost is 0, 1 and 2. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Add asm check. * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
37 lines
1.7 KiB
C
37 lines
1.7 KiB
C
/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */
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#include "vx_binary.h"
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#define T int64_t
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DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY)
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DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY)
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DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY)
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DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY)
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DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY)
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DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY)
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DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY)
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DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY)
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DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY)
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DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY)
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DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY)
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DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY)
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DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY)
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DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY)
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DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY)
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/* { dg-final { scan-assembler {vadd.vx} } } */
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/* { dg-final { scan-assembler {vsub.vx} } } */
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/* { dg-final { scan-assembler {vrsub.vx} } } */
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/* { dg-final { scan-assembler {vand.vx} } } */
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/* { dg-final { scan-assembler {vor.vx} } } */
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/* { dg-final { scan-assembler {vxor.vx} } } */
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/* { dg-final { scan-assembler {vmul.vx} } } */
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/* { dg-final { scan-assembler {vdiv.vx} } } */
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/* { dg-final { scan-assembler {vrem.vx} } } */
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/* { dg-final { scan-assembler {vmax.vx} } } */
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/* { dg-final { scan-assembler {vmin.vx} } } */
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/* { dg-final { scan-assembler-not {vsadd.vx} } } */
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/* { dg-final { scan-assembler-not {vssub.vx} } } */
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