From fa5c4be55aab8a30a6cf63752abbc955e34ecd32 Mon Sep 17 00:00:00 2001 From: Maxim Kuvyrkov Date: Mon, 5 Feb 2007 13:14:20 +0000 Subject: [PATCH] re PR target/29682 (ICE: in change_pattern, at haifa-sched.c:4066 with -O3 -msched-control-spec) PR target/29682 * config/ia64/ia64.c (ia64_speculate_insn): Restrict to memory loads to general or fp registers. Add comments. * config/ia64/ia64.md (reg_pred_prefix): Add comment. PR target/29682 * gcc-target/ia64/pr29682.c: New test. From-SVN: r121599 --- gcc/ChangeLog | 7 +++++++ gcc/config/ia64/ia64.c | 16 ++++++++++++++-- gcc/config/ia64/ia64.md | 3 +++ gcc/testsuite/ChangeLog | 5 +++++ 4 files changed, 29 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5e82b49972f6..98c59a867993 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2007-02-02 Maxim Kuvyrkov + + PR target/29682 + * config/ia64/ia64.c (ia64_speculate_insn): Restrict to memory loads to + general or fp registers. Add comments. + * config/ia64/ia64.md (reg_pred_prefix): Add comment. + 2007-02-04 Richard Guenther Backport from mainline: diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index f43b66e0c6a0..73170c8066c5 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -6807,13 +6807,19 @@ ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat) if (GET_CODE (pat) == COND_EXEC) pat = COND_EXEC_CODE (pat); + /* This should be a SET ... */ if (GET_CODE (pat) != SET) return -1; + reg = SET_DEST (pat); - if (!REG_P (reg)) + /* ... to the general/fp register ... */ + if (!REG_P (reg) || !(GR_REGNO_P (REGNO (reg)) || FP_REGNO_P (REGNO (reg)))) return -1; - mem = SET_SRC (pat); + /* ... from the mem ... */ + mem = SET_SRC (pat); + + /* ... that can, possibly, be a zero_extend ... */ if (GET_CODE (mem) == ZERO_EXTEND) { mem = XEXP (mem, 0); @@ -6822,6 +6828,7 @@ ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat) else extend_p = false; + /* ... or a speculative load. */ if (GET_CODE (mem) == UNSPEC) { int code; @@ -6838,8 +6845,12 @@ ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat) mem = XVECEXP (mem, 0, 0); gcc_assert (MEM_P (mem)); } + + /* Source should be a mem ... */ if (!MEM_P (mem)) return -1; + + /* ... addressed by a register. */ mem_reg = XEXP (mem, 0); if (!REG_P (mem_reg)) return -1; @@ -6856,6 +6867,7 @@ ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat) extract_insn_cached (insn); gcc_assert (reg == recog_data.operand[0] && mem == recog_data.operand[1]); + *new_pat = ia64_gen_spec_insn (insn, ts, mode_no, gen_p != 0, extend_p); return gen_p; diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index f25ad76be16e..e573c55653c4 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -474,6 +474,9 @@ (define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")]) +;; Define register predicate prefix. +;; We can generate speculative loads only for general and fp registers - this +;; is constrainted in ia64.c: ia64_speculate_insn (). (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")]) (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8c44bd2d68ab..81ef383e41e2 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2007-02-05 Maxim Kuvyrkov + + PR target/29682 + * gcc-target/ia64/pr29682.c: New test. + 2007-02-04 Richard Guenther Backport from mainline: